University of Illinois Urbana–Champaign
B.S. Electrical & Computer Engineering · Minor in Computer Science
Dean’s List (Fall 2024, Fall 2025, Spring 2026) · James Scholar Honors · Eta Kappa Nu (HKN)
2024 — 2028GPA 3.94 / 4.00
Resume · 2026/FPGA · RTL · IC Design
YIBO HOU / HARDWARE ENGINEER
Fromtransistor-level cellsto real-timedigital systems
Electrical & Computer Engineering student at UIUC designing digital hardware, custom silicon, and high-performance embedded systems.
01 / Foundation
Education
Recognition
Scholarships & Awards
ECE ScholarshipGrainger Engineering Achievement ScholarshipJustin David Cunningham Memorial Award
02 / Selected work
Hardware projects
Five systems spanning RTL architecture, board-level validation, custom VLSI, and analog circuit design.
01
FPGA Limit Order Book
Mar 2026 — Aug 2026
- Architected a price-time-priority matching engine with an 8,191-order BRAM pool and 4-way hash table.
- Implemented serialized Fast and Drain FSM paths with a register-resident crossing-ADD bypass and parallel bid/ask memory reads.
- Unified a 32-byte protocol across 1 Gbps UDP/RGMII, synthesizable RTL, and a bit-exact Python reference model.
- Built a Questa UVM scoreboard and passed a paced 1,000-command board stress test with 100% ACK success.
Price-Time Priority Matching1 Gbps UDP / RGMII (YT8511)Python Golden Model
Core metrics & estimates
- 125 MHz
- Core Clock Frequency
- ≈9 Cycles
- First-Trade Latency
- 8,191 Orders
- Order Capacity
- ≈9.6M Cmds/s
- Max Core Throughput (Est.)
Diagnostic first-trade latency. Estimated core throughput: 13 cycles per Fast ADD, one partial fill, no backpressure.
02
Artix-7 FPGA Graphics Engine
Sep 2025 — Jan 2026
- Architected a graphics subsystem from MicroBlaze game control and a handwritten tile/sprite renderer through AXI4-Stream/VDMA to custom TMDS/HDMI output.
- Used triple RGB565 frame buffering and frame-boundary switching to decouple rendering from scanout and prevent tearing.
- Designed a stall-safe, BRAM-backed renderer for a 128×64 tile map and sixteen 32×32 sprites.
- Integrated FAT32 SD-card assets, UART input, an asynchronous pixel FIFO, and OSERDESE2-based TMDS transmission.
SystemVerilog RTL RendererMicroBlaze Game ControlAXI VDMA + DDR3720p TMDS HDMI
Measured outcome
- 1280 × 720p60
- HDMI Output
- Triple Buffer
- Frame Buffering
- 16 Sprites
- RTL Renderer
- +0.848 ns WNS
- Timing Closure
03
AD/DA UDP Oscilloscope & Waveform Generator
May 2026 — Aug 2026
- Built a processor-free ADC-to-UDP pipeline and host-controlled DAC return path around custom UDP/IP/RGMII RTL.
- Crossed 25/125 MHz clock domains with Gray-code asynchronous FIFOs and added dynamic ARP and automatic link recovery.
- Packetized 736 ADC samples into 1,472-byte UDP payloads, buffered 4,096 DAC samples in BRAM, and developed an interface for live display, telemetry, and waveform upload.
- Sustained zero packet loss across roughly 45 billion samples and closed post-route timing at +0.145 ns WNS.
Xilinx Artix-7 FPGA25 MSPS ADC & AD9708 DAC1 Gbps UDP & Dynamic ARP
Measured outcome
- 25 MSPS
- ADC Sampling Speed
- 1 Gbps UDP
- Gigabit Ethernet
- 4096 Samples
- DAC Waveform Memory
- Dynamic ARP
- Network Discovery
04
RISC-V ASIC & Custom VLSI Flow
Jan 2026 — May 2026
- Designed transistor-level CMOS standard cells in FreePDK45, completed DRC/LVS, and generated LEF/Liberty views.
- Manually laid out and verified the ALU, comparator, barrel shifter, and register-file macros.
- Completed full-chip Innovus place-and-route with 32 register-file hard macros, power rings, and power stripes.
Custom CMOS Cells32-bit RISC-V DatapathDRC · LVSLEF / LibertyCadence Virtuoso & Innovus
Measured outcome
- 13 Cells
- Custom Cells
- 32-bit
- RISC-V Datapath
- Register File
- Hard Macro
- Full CPU PnR
- Physical Design
05
Custom Folded-Cascode LDO Regulator
Jan 2026 — May 2026
- Designed a transistor-level 1.2 V LDO with a PMOS-input folded-cascode error amplifier, resistive feedback, and compensation network.
- Achieved a 1.27–1.29 MHz unity-gain frequency and characterized line regulation and PSR from 1 kHz to 1 MHz across load conditions.
Folded-Cascode OTATSMC 180 nm PDKgm/ID SizingLoop StabilityCadence Virtuoso & Spectre
Measured outcome
- 1.2 V
- Regulated Output
- 83.1 dB
- DC Loop Gain
- 75.22°–84.39°
- Phase Margin
- 1.27–1.29 MHz
- Unity-Gain Freq.
03 / In practice
Experience & research
Tianyi Transportation Technology, China Telecom
Systems Engineering Intern
May 2025 — Aug 2025
Suzhou, China
- Developed ROS 2 radar stress-test and monitoring tools with real-time frame-loss diagnostics, reducing manual logging time by 60%.
- Migrated a millimeter-wave radar driver from UDP to CAN; validated multiple LiDAR systems and cross-sensor timing with IEEE 802.1AS PTP, NTP, and GPS.
- Deployed offline Docker images from IPv6 registries for containerized radar and LiDAR perception pipelines.
Cunjiang Yu Research Group, UIUC
Research Assistant · 15 hrs/week
Feb 2025 — Present
Urbana, IL
- Designed silicon microelectrode arrays and microparticles for retinal prosthesis, cardiac pacing, and neural-stimulation research.
- Fabricated and characterized 200 µm NIP semiconductor electrodes to evaluate retinal-prosthesis performance.
04 / Toolchain
Technical skills
Capability map
Hardware engineering toolchain
01
Domain 01
HDL & Verification
- SystemVerilog
- Verilog
- UVM
- Questa
- VCS / Verdi
02
Domain 02
FPGA & Digital Design
- Vivado / Vitis
- AXI4 / AXI4-Stream
- CDC
- BRAM
- DDR3
- Asynchronous FIFOs
03
Domain 03
IC Tools & Programming
- Cadence Virtuoso
- Innovus
- Spectre
- Ethernet / RGMII / UDP
- Tcl
- C / C++
05 / Coursework
Coursework
Built on the full hardware stack.
Core study across computer architecture, digital and analog ICs, FPGA systems, devices, and software foundations.
ECE 411Ongoing
Computer Organization & Design
ECE 482Ongoing
Digital IC Design
ECE 483
Analog IC Design
ECE 425
VLSI System Design
ECE 385
Digital Systems Laboratory
ECE 340
Semiconductor Devices
ECE 310
Digital Signal Processing
CS 225
Data Structures