ALIENTEK DaVinci Pro CF7A100B
Artix-7 XC7A100T platform with 512 MiB DDR3, HDMI_B output, SD card, and UART/JTAG bring-up interfaces.
Board: ALIENTEK DaVinci Pro CF7A100B•FPGA: Artix-7 XC7A100T-2FGG484
Artix-7 FPGA Platformer Engine
A 1280×720p60 platform game combining a handwritten SystemVerilog tile/sprite renderer with MicroBlaze gameplay control. Frames move through AXI4-Stream and VDMA into DDR3 triple buffers, then cross into a custom TMDS HDMI transmitter; maps, collision data, tiles, sprites, and palettes load from an SD card.
SystemVerilog RTL RendererMicroBlaze Game ControlAXI VDMA + DDR3720p TMDS HDMISD / FAT32 + UART
HDMI OUTPUT
1280 × 720p60
RGB565 · 74.25 MHz pixel clockFRAME BUFFERING
Triple Buffer
AXI VDMA · 2 MiB-aligned storesRTL RENDERER
16 Sprites
32×32 sprites · 128×64 tilemapTIMING CLOSURE
+0.848 ns WNS
Post-route implementation metMEDIA GALLERYPhysical target and on-board gameplay
01. Hardware Setup & Gameplay Demo
The DaVinci Pro target board, the DDR-rendered level selector, and the complete FPGA gameplay demonstration.
DDR3 Level Selection Screen
MicroBlaze verifies SD assets, draws the three-card selector into DDR3, and accepts A/D plus Space input over UART.
FPGA Gameplay Demo
SD-loaded assets, UART keyboard control, DDR3 frame buffers, and HDMI output running on the Artix-7 board.
02. System Architecture & Frame Dataflow
The renderer is handwritten RTL, gameplay and asset management run on MicroBlaze, and Xilinx IP supplies the memory, DMA, processor, and peripheral infrastructure.
FRAME-BASED GAME PIPELINE
Inputs → Sprite Render → DDR3 → HDMI
HOST INPUTPC KeyboardUART key-state byte
STORAGESD CardSPI assets · maps · sprites
100 MHz MIG UI / AXI74.25 MHz pixel371.25 MHz TMDS 5×
CONTROL PLANEMicroBlazeGameplay · assets · VDMA
HANDWRITTEN RTLSprite EngineTilemap + 16 sprites
VIDEO STREAMAXI4-StreamTUSER · TLAST · RGB565
FRAME STOREVDMA + DDR3Triple buffering
CLOCK CROSSINGAsync FIFOAXI UI → pixel clock
VIDEO OUTPUTTMDS / HDMI1280 × 720 @ 60 Hz
RTL Design
- Sprite renderer
- AXI4-Stream pipeline
- TMDS encoder
- CDC handling
Software Control
- Gameplay state logic
- SD asset management
- UART keyboard input
- VDMA frame control
Platform Infrastructure
- DDR3 MIG
- AXI interconnect
- VDMA
- Clock / reset
03. SD-Card Assets & Level Maps
The FAT32 SD image supplies maps, collision data, tiles, sprites, and an RGB565 palette. Each preview below is generated from the same 128×64-tile data consumed by the FPGA renderer.
Copper Hills
Level 01 · 2048×1024 generated world preview
Sky Bridges
Level 02 · 2048×1024 generated world preview
Starfall Run
Level 03 · 2048×1024 generated world preview