FPGA Limit Order Book
Serialized FSM price-time-priority matching engine for Artix-7 with a crossing-ADD fast path, BRAM-backed book state, UDP transport, and Python/UVM verification.
Technologies:Matching EngineQuesta UVMUDP / RGMII
FPGA / RTL / ASIC · UIUC ECE
Projects
Hardware design projects spanning digital systems, FPGA/ASIC implementation, and IC design.
Digital Hardware
Custom FPGA systems and RTL designs featuring high-speed interfaces, memory systems, and hardware pipelines.
FPGA Graphics Engine
Hardware graphics pipeline for Artix-7 combining sprite rendering, DDR3 framebuffer management, and 720p60 HDMI output.
Technologies:TMDS HDMIDDR3 MIGSD card I/O
AD/DA UDP Oscilloscope
Custom FPGA Ethernet acquisition platform with ADC sampling, UDP streaming, ARP resolution, and DAC waveform playback on Xilinx Artix-7.
Technologies:Ethernet MACUDP/IPRGMIIADC / DAC
Integrated Circuit Design
IC design projects spanning RTL synthesis, physical design, and analog circuit implementation.
RISC-V ASIC & Custom VLSI Flow
Custom CMOS standard-cell library, 32-bit bit-sliced RISC-V datapath, and full CPU synthesis and physical design with a register-file hard macro.
Technologies:Custom CMOSRISC-V DatapathLEF / LibertyCadence PnR
Folded-Cascode LDO Regulator
Transistor-level LDO regulator with a PMOS-input folded-cascode amplifier, feedback loop, and stability optimization in Cadence Virtuoso.
Technologies:Folded CascodeLDO Stabilitygm/ID SizingCadence Virtuoso