YH
YIBO HOUECE @ UIUC • HARDWARE ENGINEER
Projects/Artix-7 FPGA Limit Order Book
Board: ALIENTEK DaVinci Pro CF7A100B•FPGA: Artix-7 XC7A100T-2FGG484

Artix-7 FPGA Limit Order Book

Pure hardware price-time-priority matching engine with serialized FSM execution, a crossing-ADD fast path, BRAM-backed book state, and an end-to-end 32-byte wire protocol. Supports live order flows over Gigabit UDP, with a Python golden model and Questa UVM testbench.

SystemVerilog RTL LogicPrice-Time Priority Matching1 Gbps UDP / RGMII (YT8511)Questa UVM VerificationPython Golden Model
View GitHub Repository→Watch Demo Video
CORE CLOCK FREQUENCY
125 MHz
8.0 ns deterministic cycle period
FIRST-TRADE LATENCY
≈9 Cycles
≈72 ns diagnostic core measurement
ORDER CAPACITY
8,191 Orders
BRAM pool + 4-way hash table
MAX CORE THROUGHPUT (EST.)
≈9.6M Cmds/s
Fast ADD · 13 cycles · single partial fill · no stalls
MEDIA GALLERYLive Hardware Setup & Video Demo

01. Hardware Setup & Video Preview

Hardware target board followed by a full-width interactive Python golden-model demo and the real-time UDP order-flow video walkthrough.

ALIENTEK DaVinci Pro FPGA Board

Artix-7 XC7A100T board running the LOB engine over Gigabit RGMII Ethernet.

ALIENTEK DaVinci Pro Artix-7 FPGA development board

Python CLI Order Book Demo

Command-line session showing the live FPGA connection and supported order operations.

Python CLI session connected to the FPGA limit order book

Python Interactive Order Book Demo

Browser mirror of software/lob/orderbook.py: issue all four commands and inspect price-time matching in real time.

PYTHON GOLDEN MODEL

Interactive limit order book

PYTHON-ALIGNED
lob> submit commandFPGA limits: 8,191 live · levels 0–4,095 · qty uint32
Source: orderbook.py ↗
LIVE ORDER BOOK6 / 8,191 live
BEST BID99
SPREAD2
BEST ASK101
BIDSPRICE   QTY   ORDERS
ASKSPRICE   QTY   ORDERS
EVENT STREAMready
price-time engine readylast trade —

Hardware Matching Engine Demo Video

Real-time UDP 32-byte datagram injection, live price matching, and trade execution reporting on Artix-7.

Open Video ↗

02. End-to-End Hardware Architecture

The implemented board path carries 32-byte commands through RGMII and UDP framing into a FIFO-buffered, serialized controller. The order manager handles book maintenance, while the matcher consumes resting orders and updates shared book state during trades. Ingress and egress can overlap core execution.

01

LIVE BOARD ORDER FLOW

UDP Order → Match or Book Update → ACK / Reports

125 MHz · 32-byte protocol · UDP :5000
FPGA order processing flowA Python host sends a UDP order to the FPGA. The FPGA buffers and decodes the command, executes matching or book maintenance through a serialized controller, builds an acknowledgement or trade report, and sends the result back over UDP.LOB_DAVINCI_PRO_TOP · ARTIX-7 XC7A100TIF CROSSEDEXECUTE reports + command ACKSOFTWAREPython Hostsend ordersreceive resultsRECEIVE UDP ORDERRGMII inputIPv4 / UDP decode32-byte ordercommand payloadMESSAGE_DECODER.SVDecode Commandunpack 32-byte fieldsbuffer + unpack fieldsLOB_ENGINE_TOPRoute Commandcommand FIFO + FSMone command at a timeMATCHER.SVExecute Matchcrossing ADD ordertrade with resting headFast ADD bypassORDER_MANAGER.SVUpdate Live Bookadd · cancel · modifyexternal executebook stays consistentLIVE ORDER BOOKorders · queues · best pricesTRADE_GENERATOR.SVBuild Responsetrade reportscommand ACKSEND UDP RESULTSACK / reportresponse framingIPv4 / UDP packetRGMII output
Complete board flow: UDP order in; ACK and trade reports out.Diagnostic Fast-Path first trade: ≈72 ns from core payload acceptance; excludes network transport.
02

ORDER BOOK STORAGE & LOOKUP

How the FPGA Stores and Updates the Live Book

8,191 live orders · 4,096 levels/side
FPGA live order book storage and update flowThe matcher reads and fills resting orders while the order manager inserts, cancels, and modifies orders. The live book is held in an order pool, per-price FIFO queues, an order ID lookup index, and a best-price tracker.MATCHER.SV · TRADE EXECUTIONRead & Fill Resting Ordersreads queue heads · writes remaining quantityORDER_MANAGER.SV · BOOK MAINTENANCEInsert, Cancel & Modifycommits ordered updates to persistent book stateLOB_ENGINE_TOP · ONE ACTIVE BOOK UPDATE AT A TIMEORDER_MEMORY.SVLive Orders + Free Slotsside · price · qty · prev / nextallocates and recycles fixed slots8,191 LIVEstores linked order nodesPRICE_LEVEL.SV × 2Per-Price FIFO QueuesBUY and SELL queues by pricehead · tail · total quantity4,096 / SIDEpreserves price-time priorityORDER_ID_TABLE.SVOrder ID Lookup Indexmaps 64-bit order ID → pool slotparallel ways reduce collisions4-WAY HASHfast cancel / modify lookupBEST_PRICE_ENCODER.SVBest Bid / Ask Trackermarks non-empty price levelshighest bid · lowest askLIVE BEST PXfeeds the matcherState flow: Order ID → slot → price FIFO → occupancy → best bid / ask.
Fixed slot links preserve FIFO price-time priority at each level.Serialized updates keep the pool, queues, ID index, and best prices consistent.

03. Two Matcher Paths for Faster Trades

Fast Path keeps a crossing ADD in registers and matches before any remainder enters the book. Drain Path clears a live book that becomes crossed after an ADD or price-changing MODIFY, using parallel bid/ask reads. Both routes use a multi-cycle FSM: fills execute sequentially, with completion time determined by cleanup, best-price refresh, and output backpressure.

MATCHER.SV · TWO FSM ROUTES

How Fast Path and Drain Path Reach a Trade

Fast bypass · Parallel reads
Matcher Fast Path and Drain PathFast Path keeps a new crossing ADD in registers while matching resting orders. Drain Path reads both live sides in parallel after an add or price-changing modify crosses the book. Both routes execute sequentially in a multi-cycle FSM.MATCHER.SV · TWO WAYS TO REACH A TRADEFROM COMMAND ROUTERNew crossing ADDmatch before its remainder enters the bookFROM ORDER MANAGERBook becomes crossedafter ADD or price-changing MODIFYFAST PATH · FSMMatch First, Store Remainder Later≈72 ns COREKEEP ORDER LOCALno initial book writeREAD BEST ORDERbest price + queue headTRADE + UPDATEenqueue if uncrossedWHY FASTERSkip slot, ID, and queue work before the first trade.DRAIN PATH · PARALLEL READSClear Crossed Orders DirectlyPARALLEL READSORDERS IN BOOKno admission workREAD BOTH SIDESbid + ask in parallelCLEAR THE CROSSrepeat until uncrossedWHY FASTERParallel reads without repeating order admission.SAME RESULT · TRADE + UPDATED LIVE BOOKserialized command executionFast Path handles a new crossing ADD; Drain Path handles a live book that becomes crossed.
FAST PATH

New crossing order

The incoming ADD remains in registers while the FSM consumes resting heads. Only a non-crossing remainder is enqueued; each fill still updates the live book.

DRAIN PATH

Already-crossed live book

The FSM reads bid and ask levels together, then both FIFO heads through the dual-port order pool. Fills and cleanup execute sequentially.

PERFORMANCE SCOPE

Latency and throughput

First trade≈9 cycles · ≈72 ns
Est. peak core≈9.6M Cmds/s
Command interval13 cycles · Fast ADD

First-trade latency is diagnostic. Core throughput estimate: 125 MHz / 13 cycles, with one partial fill per Fast ADD and no backpressure.

04. Frozen 32-Byte Wire Protocol

The Python model, UVM scoreboard, and synthesizable RTL share the exact big-endian binary frame format for seamless verification and live hardware networking.

Byte OffsetField NameSizeData TypeDescription & Encodings
0version1 byteuint8Protocol version 0x01
1msg_type1 byteuint80x01 ADD · 0x02 CANCEL · 0x03 MODIFY · 0x04 EXECUTE
2side1 byteuint80x00 BUY · 0x01 SELL
3flags1 byteuint8bit0 FLAG_EXTERNAL=0x01; all other bits reserved=0
4–7seq_num4 bytesuint32_beSender-monotonic sequence number (starts at 1)
8–15order_id8 bytesuint64_beClient order ID
16–19price4 bytesuint32_beFixed-point price; current supported range 1–4095
20–23quantity4 bytesuint32_be> 0 for ADD, MODIFY, and external EXECUTE; unused by CANCEL
24–31timestamp_ns8 bytesuint64_beNanosecond timestamp

05. Board Validation & Verification Results

Paced UDP board stress, full 8,191-order live capacity, and post-implementation timing closure at 125 MHz.

BOARD VALIDATIONUDP stress and full live-order capacity verified on Artix-7
FPGA Board Stress1,000 paced UDP commands100% ACK success · reference matched
Live-Order Capacity8,191 orders acceptedOrder 8,192 rejected as full
Timing Closure @ 125 MHzWNS +0.001 ns · WHS +0.035 nsPost-implementation met
UVM VERIFICATION

Questa UVM Scoreboard

QuestaSim scoreboard: sweep, ACK, and defensive checks passed.

RECORDED RUN · PASS
0Hardware errors
100%Verification passed
Main Test Categories

Fast-Path Crossing

Aggressive ADD orders sweep resting asks across multiple price levels.

Cancel & Modify

Hash lookup, linked-list splice, quantity updates, and slot release.

Mixed Stress Flow

Crossing adds, passive orders, cancels, and modifies in one realistic stream.

Boundary Defense

Duplicate IDs, invalid prices, zero quantity, and minimum/maximum levels.

Questa UVM waveform showing three fast-path trades as the best ask moves from 100 to 101 to 102 and then empty
Questa waveform reference for the multi-level fast-path sweep; observed outputs are scoreboard-verified.
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