FPGA Limit Order Book
Serialized FSM price-time-priority matching engine for Artix-7 with a crossing-ADD fast path, BRAM-backed book state, UDP transport, and Python/UVM verification.
Technologies:Matching EngineQuesta UVMUDP / RGMII
ECE Student @ UIUC•Targeting Hardware Engineering Internships & Full-Time
Yibo Hou
Digital Hardware Systems • RTL Design • IC Design
Electrical & Computer Engineering (ECE) student at the University of Illinois Urbana-Champaign (UIUC). Focused on digital hardware architecture, synthesizable RTL design, FPGA systems, ASIC design flows, and analog circuit development.
Hardware PortfolioSelected RTL & Systems
Featured Hardware Engineering Projects
FPGA systems featuring custom RTL design, high-speed interfaces, and hardware validation.
Technical ProfileDigital & Mixed-Signal Hardware
Hardware Design Domains
Synthesizable RTL, ASIC implementation flows, and system-level hardware architecture.
01 · RTL SYSTEMS
FPGA & RTL Design
Synthesizable SystemVerilog for complete FPGA systems. CDC, asynchronous FIFOs, timing constraints, clock management, and hardware validation.
02 · DIGITAL & ANALOG IC
Integrated Circuit Design
Digital and analog IC design spanning RTL-to-layout flows, standard-cell implementation, transistor-level circuits, and simulation-based verification.
03 · SYSTEM ENGINEERING
Hardware Architecture
Hardware system design covering high-throughput datapaths, memory interfaces, and custom accelerators with AXI, DDR3, HDMI, and Ethernet integration.
Research · ExperienceTechnical Experience
Internship & Research
Exploring Hardware Systems from Silicon to Embedded Platforms
Industry ExperienceMay–Aug 2025
Tianyi Transportation · China Telecom
Systems Engineering Intern
Suzhou, China
- Built ROS 2 radar stress-test and monitoring tools with real-time frame-loss diagnostics, reducing manual logging time by 60%.
- Migrated radar transport from UDP to CAN and validated LiDAR deployment, multi-sensor time synchronization, and containerized perception pipelines.
Academic ResearchFeb 2025–Present
Cunjiang Yu Research Group · UIUC
Research Assistant
Urbana, Illinois
- Designed silicon microelectrode arrays and microparticles for retinal prostheses, cardiac pacing, and neural stimulation.
- Fabricated and characterized 200 μm NIP semiconductor electrodes to evaluate retinal-prosthesis performance.
EducationGrainger Engineering · ECE @ UIUC
Academics & Honors
University of Illinois Urbana-Champaign (UIUC)
Bachelor of Science in Electrical & Computer Engineering
Relevant Core ECE Coursework
Full List of ECE CourseworkECE 411Computer Org & Design
Pipelined RISC-V processor architecture, out-of-order execution, branch prediction, cache hierarchy, and SystemVerilog verification.
ECE 482Digital IC Design
CMOS digital circuit design, standard-cell implementation, timing analysis, and physical design considerations for integrated systems.
ECE 483Analog IC Design
MOS and bipolar analog design techniques, operational amplifiers, feedback amplifiers, oscillators, and circuit noise.
ECE 425Intro to VLSI System Design
CMOS logic and layout, circuit characterization, VLSI CAD tools, and custom chip design using hierarchical design methods.
ECE 385Digital Systems Lab
SystemVerilog RTL design, FPGA synthesis, HDMI TMDS video timing, and hardware debugging with Vivado.
ECE 340Semiconductor Devices
Semiconductor fundamentals, MOSFETs, PN junctions, bipolar transistors, charge transport, and device-level circuit behavior.
Recognition
Honors & Awards
Electrical & Computer Engineering Scholarship
Grainger Engineering Achievement Scholarship
Justin David Cunningham Memorial Award
Dean's List
James Scholar Honors Program
Involvement
Professional Societies & Activities
Eta Kappa Nu (HKN)
Honor SocietyElectrical & Computer Engineering Honor Society
IEEE
Institute of Electrical and Electronics Engineers
Eco Illini Supermileage
Student engineering and vehicle-efficiency team