YH
YIBO HOUECE @ UIUC • HARDWARE ENGINEER
Projects/RISC-V ASIC & Custom VLSI Flow
Course: ECE 425 · VLSI System Design•Flow: Custom CMOS → RISC-V Datapath → ASIC PnR

RISC-V ASIC & Custom VLSI Flow

A bottom-up digital IC design project featuring a fully custom 32-bit single-cycle bit-sliced RISC-V datapath with a hand-built shifter, transistor-level CMOS standard cells, and RTL-to-layout ASIC flow. Custom LEF/Liberty views enable full-chip place-and-route with integrated register-file hard macros.

Custom CMOS CellsFreePDK4532-bit RISC-V DatapathVCS / VerdiDRC · LVSLEF / LibertyCadence Virtuoso & Innovus
View GitHub Repository
CUSTOM CELLS
13 Cells
DRC · LVS
RISC-V DATAPATH
32-bit
Bit-sliced RTL
HARD MACRO
Register File
Macro Embedded
PHYSICAL DESIGN
Full CPU PnR
Std-cell + Macro
CUSTOM LIBRARYTransistor-level design through physical verification

01. CMOS Standard-Cell Foundation

Combinational, storage, and multiplexing primitives were designed with consistent power rails, well structures, cell height, and routing access, then packaged as reusable LEF and Liberty views.

D Flip-Flop Layout

Custom storage cell with shared rails and physical routing layers.

Custom CMOS D flip-flop physical layout

2:1 Multiplexer Layout

Reusable mux primitive from the verified custom cell library.

Custom CMOS two-to-one multiplexer physical layout

Select a cell group to inspect the physical layouts.

02. Bit-Sliced RISC-V Datapath

The custom cells scale into a regular 32-bit datapath containing the ALU, register file, PC path, comparison logic, memory muxing, and an extra-credit shift-capable variant.

ALU Physical Layout

Verified arithmetic and logic block used by the repeated bit-slice structure.

Custom RISC-V arithmetic logic unit physical layout

Datapath with Shifter

Extra-credit shift-capable 32-bit physical implementation

32 repeated bit slices
Full 32-bit bit-sliced RISC-V datapath physical layout with shifter

03. ASIC Synthesis & Physical Design

Custom cell abstracts feed the automated flow from controller PnR to a complete CPU, followed by a second implementation that places 32 register-file hard macros across the bit-sliced datapath.

Controller PnR

Synthesized controller with power ring, stripes, placement, and routed interconnect.

Controller PnR physical design view

Standard-Cell CPU

Full CPU implementation built from the exported custom standard-cell library.

Standard-Cell CPU physical design view

Register-File Macro CPU

Full CPU floorplan integrating 32 placed register-file hard macros.

Register-File Macro CPU physical design view
LIBRARY EXPORT
stdcells.lef / .lib
HARD MACRO
regfile.lef / .lib
POWER DELIVERY
Rings + vertical stripes
ROUTING
Metal 1–6 signal stack