YH
YIBO HOUECE @ UIUC • HARDWARE ENGINEER
Projects/Artix-7 AD/DA UDP Oscilloscope
Board: ALIENTEK DaVinci Pro CF7A100B•FPGA: Artix-7 XC7A100T-2FGG484

Artix-7 AD/DA UDP Oscilloscope

Hardware-only UDP acquisition and waveform playback engine for Xilinx Artix-7 FPGAs. Streams 8-bit ADC samples at 25 MSPS over Gigabit Ethernet (1000BASE-T) and accepts DAC waveform tables with dynamic ARP MAC resolution — implemented completely in pure SystemVerilog RTL without soft processors or OS overhead.

SystemVerilog RTL LogicXilinx Artix-7 FPGA25 MSPS ADC & AD9708 DAC1 Gbps UDP & Dynamic ARPPySide6 Oscilloscope GUI
View GitHub Repository→Watch Demo Video
ADC Sampling Speed
25 MSPS
8-bit AD9280 ADC Converter
GIGABIT ETHERNET
1 Gbps UDP
YT8511 · RGMII
DAC WAVEFORM MEMORY
4096 Samples
8-bit Waveform BRAM
NETWORK DISCOVERY
Dynamic ARP
Automatic Host MAC Learning
MEDIA GALLERYLive Hardware Setup & Video Demo

01. Hardware Setup & Video Preview

Side-by-side hardware board setup photos followed by the real-time oscilloscope video demonstration.

DaVinci Pro Board with AD/DA Module

Artix-7 XC7A100T development board connected to host PC over Gigabit RGMII Ethernet.

DaVinci Pro board with AD/DA module

AD/DA Conversion Extension Module

Dual-conversion module integrating AD9280 8-bit ADC (25 MSPS) & AD9708 8-bit DAC (50 MHz).

AD/DA module closeup

Hardware Demo Video

Real-time ADC capture & DAC playback in PySide6 GUI

Open Video ↗

PySide6 Oscilloscope & Waveform Control UI

Live ADC trace, UDP telemetry, and DAC waveform upload controls in one desktop view.

PySide6 desktop oscilloscope UI displaying a captured sine wave, real-time UDP statistics, and AD9708 DAC waveform controls

02. End-to-End Hardware Dataflow

Bi-directional high-frequency data pipelines: streaming high-speed ADC samples to host PC via UDP, and uploading custom waveform LUTs to the DAC player.

01

UPLINK · ACQUISITION

ADC sample stream → desktop scope

25 MSPS · UDP :5000
ADC acquisition dataflowAnalog input flows through an ADC, capture logic, asynchronous FIFO, packetizer and UDP stack before reaching the PySide6 oscilloscope.ARTIX-7 FPGA · STREAMING TX PATHANALOG INPUTAD9280 ADC8-bit · 25 MHzSAMPLING DOMAINADC CaptureSync registerCDC BRIDGEAsync FIFO25 → 125 MHzFRAMINGPacketizer736 samples / pktNETWORKIPv4/UDPRGMII TXHOST PCPySide6 ScopeLive waveform renderclock crossing1 GbE / ARPContinuous 8-bit samples move left → right; control traffic is kept off this real-time transmit lane.
02

DOWNLINK · PLAYBACK

Waveform command → analog output

4,096 samples · UDP :5001
DAC waveform playback dataflowHost commands enter through RGMII and a UDP parser, write waveform data to block RAM, then the DAC player produces analog output.ARTIX-7 FPGA · WAVEFORM RX PATHHOST PCPySide6 AppLOAD · PLAY · STOPPHY RECEIVERYT8511 RGMIIGigabit link RXPROTOCOLUDP EngineCommand decoderWAVEFORM STOREBlock RAM4096 × 8-bitPLAYBACKDAC Player50 MHzANALOG OUTPUTAD9708 DACCustom waveform16-byte command header8-bit DACCommands and LUT data move left → right; the BRAM isolates upload traffic from the fixed-rate DAC player.

03. Hardware Validation

Extended DA-to-AD coax loopback validation on the target board, including network discovery and link recovery.

HARDWARE VALIDATEDContinuous UDP acquisition and DAC loopback on the physical target
Extended soak run≈30 minutes
UDP stream rate~34,200 packets/sZero packet loss
ADC volume @ 25 MSPS≈45B samples
Network discoveryDynamic ARP learningAutomatic host MAC learning
Link recovery3× disconnect / reconnectAutomatic recovery
Timing closureWNS +0.145 ns · WHS +0.044 ns