Projects/Folded-Cascode LDO Regulator
Course: ECE 483 · Analog IC Design•Spring 2025

Folded-Cascode LDO Regulator

A transistor-level CMOS low-dropout regulator featuring a PMOS-input folded-cascode error amplifier and PMOS pass device. The design applies gm/ID-based transistor sizing, feedback compensation, and stability optimization to achieve robust gain and phase margin across operating conditions.

Folded-Cascode OTATSMC 180 nm PDKgm/ID SizingLoop StabilityCadence Virtuoso & Spectre
REGULATED OUTPUT
1.2 V
From a nominal 1.8 V input
DC LOOP GAIN
83.1 dB
At 1 mA and 25 mA load
PHASE MARGIN
75.22°–84.39°
Stable across load conditions
UNITY-GAIN FREQ.
1.27–1.29 MHz
Across evaluated load points
ARCHITECTUREFeedback, gain, and pass-device integration

01. Transistor-Level LDO Design

A 0.6 V reference and resistive feedback establish the 1.2 V output. A PMOS-input folded-cascode amplifier provides high loop gain while avoiding the parasitic penalty of the initial OTA design.

Complete LDO Schematic

Folded-cascode error amplifier, compensation network, PMOS pass transistor, and resistive feedback.

Transistor-level folded-cascode LDO schematic

02. Loop-Gain Stability

AC loop-gain verification showed approximately 83.1 dB DC gain, 1.27–1.29 MHz unity-gain frequency, and phase margin above 75° across the evaluated load points.

Minimum-Load Loop Gain

Low-load stability with the output-resistance limiting network active.

Minimum-Load Loop Gain

Maximum-Load Loop Gain

High-load loop response and gain-margin verification.

Maximum-Load Loop Gain

03. DC Regulation

The regulator achieved 6 µV/mA DC load regulation and 479 µV/V / 128 µV/V line regulation at the reported light- and high-load conditions, meeting the project limits.

Line Regulation

Output response over the 1.68 V to 1.98 V input sweep.

Line Regulation

Load Regulation

Regulated output across the evaluated load-current sweep.

Load Regulation

04. Power-Supply Rejection

PSR was characterized from 1 kHz to 1 MHz under light-load and full-load conditions to quantify how supply ripple propagates to the regulated output.

Light-Load PSR

Supply-rejection response at 0.1 mA load current.

Light-Load PSR

Full-Load PSR

Supply-rejection response at 25 mA load current.

Full-Load PSR